Logic Design Manager
Organization & Role The Logic Design Manager is responsible for leading a team of developers in designing and verifying FPGA's and digital ASIC IP for Teradyne Semiconductor Test Division's next generation products.
In this role you will lead a team of 4-6 engineers in a fast-paced environment to help the organization meet key business needs.
Requires close collaboration with the other FPGA design and verification managers and with other engineering disciplines including mixed signal ASIC design, circuit board design, software and systems engineering to specify and implement new products.
You should have hands-on experience with complex FPGA (and preferably digital ASIC) SOC designs for real-world products.
You also should have a proven track record of managing engineering teams toward timely deliverables and successful project completion.
This is a hybrid position in our North Reading, MA headquarters.
Responsibilities Lead multiple simultaneous (typically 2-3) FPGA or digital IP development projects.
Typically includes oversight of some remote resources.
Planning and tracking of project schedule and budget.
Manage project staffing levels including both full time and contract resources.
Represent the FPGA/IP team on project core teams and at program reviews.
Contribute to FPGA/IP implementation (i.
e.
code RTL blocks) as needed.
Provide technical support for HW sustaining issues.
Set goals, provide coaching and manage compensation of a 4-6 person team.
Contribute to FPGA/IP team process improvement initiatives.
Collaborate with other engineering and business disciplines to ensure that FPGA and IP deliverables satisfy all product requirements.
Basic Qualifications & Skills Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation and lab validation to production release.
3 years of experience as a first level manager of an engineering team.
Extensive experience coding RTL (Verilog preferred).
Extensive experience using digital simulation tools (Cadence preferred).
Extensive experience using static timing analysis tools.
Experience designing with the following:
PCIe, DDR3/4, AXI, ethernet, SPI, SERDES Experience using digital design quality tools e.
g.
, LINT, CDC, LEC.
Experience with either Xilinx or Intel FPGAs and development tools, preferably both.
Experience with bug tracking tools (Jira, Bugzilla etc.
) Experience with source control systems (ClearCase, Git, CVS) and continuous integration.
Familiarity with digital verification tools and methodologies (preferably UVM).
Experience with project scheduling tools (e.
g.
Microsoft project) Experience with embedded processors and digital signal processing is a plus.
Experience with high level programming languages (C, C++) is a plus.
Experience developing hardware for automated test equipment Education BSEE or MSEE and 12
years of relevant experience in Digital FPGA design and integration (Digital ASIC experience is a plus).
Recommended Skills Advanced Microcontroller Bus Architecture Architecture Automatic Test Equipment Bug Tracking Bugzilla Business Process Improvement Estimated Salary: $20 to $28 per hour based on qualifications.
In this role you will lead a team of 4-6 engineers in a fast-paced environment to help the organization meet key business needs.
Requires close collaboration with the other FPGA design and verification managers and with other engineering disciplines including mixed signal ASIC design, circuit board design, software and systems engineering to specify and implement new products.
You should have hands-on experience with complex FPGA (and preferably digital ASIC) SOC designs for real-world products.
You also should have a proven track record of managing engineering teams toward timely deliverables and successful project completion.
This is a hybrid position in our North Reading, MA headquarters.
Responsibilities Lead multiple simultaneous (typically 2-3) FPGA or digital IP development projects.
Typically includes oversight of some remote resources.
Planning and tracking of project schedule and budget.
Manage project staffing levels including both full time and contract resources.
Represent the FPGA/IP team on project core teams and at program reviews.
Contribute to FPGA/IP implementation (i.
e.
code RTL blocks) as needed.
Provide technical support for HW sustaining issues.
Set goals, provide coaching and manage compensation of a 4-6 person team.
Contribute to FPGA/IP team process improvement initiatives.
Collaborate with other engineering and business disciplines to ensure that FPGA and IP deliverables satisfy all product requirements.
Basic Qualifications & Skills Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation and lab validation to production release.
3 years of experience as a first level manager of an engineering team.
Extensive experience coding RTL (Verilog preferred).
Extensive experience using digital simulation tools (Cadence preferred).
Extensive experience using static timing analysis tools.
Experience designing with the following:
PCIe, DDR3/4, AXI, ethernet, SPI, SERDES Experience using digital design quality tools e.
g.
, LINT, CDC, LEC.
Experience with either Xilinx or Intel FPGAs and development tools, preferably both.
Experience with bug tracking tools (Jira, Bugzilla etc.
) Experience with source control systems (ClearCase, Git, CVS) and continuous integration.
Familiarity with digital verification tools and methodologies (preferably UVM).
Experience with project scheduling tools (e.
g.
Microsoft project) Experience with embedded processors and digital signal processing is a plus.
Experience with high level programming languages (C, C++) is a plus.
Experience developing hardware for automated test equipment Education BSEE or MSEE and 12
years of relevant experience in Digital FPGA design and integration (Digital ASIC experience is a plus).
Recommended Skills Advanced Microcontroller Bus Architecture Architecture Automatic Test Equipment Bug Tracking Bugzilla Business Process Improvement Estimated Salary: $20 to $28 per hour based on qualifications.
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